Publications

SoC-e has a strong R&D activity and maintains a strong link with the Applied Electronics Research Team (APERT) of the University of the Basque Country (UPV/EHU) . Some of the topics covered by this research are the following:

  • Self-reparable systems based on FPGAs.
  • SoPC and architectures for communications, video, security and control.
  • Dynamic reconfiguration based on SRAM FPGAs.

SoC-e collaborates with different Universities and Research Centers to contribute to the research community enhancing the technologies related to reliable networking, synchronization and security.

The following publication list summarizes some of the publications released with SoC-e support:

 

2016 Scientific-Technical Contributions:

IEEE TRANSACTIONS ON SMART GRID

Title

On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems

Abstract

A synchronized common sense of time is a key factor for many smart grid applications, such as the sample value process bus operation. The precision time protocol (PTP), as defined in IEEE 1588-2008 standard, is highly recommended for substation communication networks, because it enables synchronization accuracies in the nanoseconds range through conventional Ethernet-based networks. This paper explores the implementation of PTP functionalities on new Xilinx Zynq-7000 all programmable system-on-chip (SoC) device. Different PTP master and slave implementations have been analyzed taking benefit from the flexibility of the SoC all programmable devices. The explored features go from simple only-software versions aided by PTP support of GMACs embedded in the processor section to high accuracy solutions that include custom PTP hardware in the logic section of the device. For each configuration approach, two different experimental setups based on two Zynq commercial low-cost boards has been built, and the protocol performance has been evaluated by measuring time offset between the pulse per second output signals of the master and the synchronized slave. The results obtained from this analysis show excellent accuracy results, with time offsets in the range of 40 ns and standard deviations of less than 10 ns.

Link

IEEEXPLORE

2015 Scientific-Technical Contributions:

2015 International IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISCPS 2015)

Title

Security Mechanisms to protect IEEE 1588 Synchronization: State of the Art and Trends

Abstract

The limitations of Annex K, as defined in the second version of IEEE 1588 standard, lead the standardization committee to evolve from an integrated security solution to a set of internal and external security mechanisms. The aim of the group is to address different requirements and deployment paradigms of application specific profiles. In this paper, a comparative study of the proposed security solutions within the working group is presented. In addition, a new MACsec use case to provide hop-by-hop group security is introduced.

Link

IEEEXPLORE

Title

1588-aware High-Availability Cyber-Physical Production System

Abstract

In this paper, an architecture for High-Availability Cyber-Physical Production Systems with sub-microsecond synchronization capabilities is presented. The proposed CPPS nodes are based on cost-affordable components. These CPPS can deal with most of the challenges set by Industry for a massive adoption of the distributed computing philosophy in critical systems like Smart-Grids or Advanced Manufacturing Plants. In order to measure the resilience and accuracy of the 1588-aware high-availability network composed by these nodes, a concept-proof experimental setup has been developed. As it has been verified, although in a case of network failure, the synchronization recovers automatically and the offset between the master’s and slaves’ PPS signals is maintained below 1 μs.

Link

IEEEXPLORE

The Scientific World Journal

Title

Availability Improvement of Layer 2 Seamless Networks Using OpenFlow

Abstract

The network robustness and reliability are strongly influenced by the implementation of redundancy and its ability of reacting to changes. In situations where packet loss or maximum latency requirements are critical, replication of resources and information may become the optimal technique. To this end, the IEC 62439-3 Parallel Redundancy Protocol (PRP) provides seamless recovery in layer 2 networks by delegating the redundancy management to the end-nodes. In this paper, we present a combination of the Software-Defined Networking (SDN) approach and PRP topologies to establish a higher level of redundancy and thereby, through several active paths provisioned via the OpenFlow protocol, the global reliability is increased, as well as data flows are managed efficiently. Hence, the experiments with multiple failure scenarios, which have been run over the Mininet network emulator, show the improvement in the availability and responsiveness over other traditional technologies based on a single active path.

Link

HINDAWI

Computer and Electrical Engineering

Title

Using Software Defined Networking to manage and control IEC 61850-based systems

Abstract

Smart Grid makes use of Information and Communications Technology (ICT) infrastructures for the management of the generation, transmission and consumption of electrical energy to increase the efficiency of remote control and automation systems. One of the most widely accepted standards for power system communication is IEC 61850, which defines services and protocols with different requirements that need to be fulfilled with traffic engineering techniques. In this paper, we discuss the implementation of a novel management framework to meet these requirements through control and monitoring tools that provide a global view of the network. With this purpose, we provide an overview of relevant Software Defined Networking (SDN) related approaches, and we describe an architecture based on OpenFlow that establishes different types of flows according to their needs and the network status. We present the implementation of the architecture and evaluate its capabilities using the Mininet network emulator.

2014 Scientific-Technical Contributions

2014 International IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISCPS 2014)

Title

Nanosecond Accuracy using SoC Platforms

Abstract

n this work, the implementation of IEEE 1588 functionalities on new Xilinx Zynq-7000 All Programmable SoC device is explored. An experimental set-up based on two Zynq commercial low-cost boards, with different PTP master and slave implementations has been analysed, taking benefit from the flexibility of the SoC all programmable devices. The explored features go from the only-software versions aided by the IEEE 1588-aware GMACs embedded in the processor sections to the high-accuracy solutions that combine the IEEE1588 hardware stuff of these modules with custom PTP IP cores in the FPGA sections of the devices. The results obtained from this analysis show excellent accuracy results, in the range of few nanoseconds and also standard deviation of less than 10 nanoseconds.

Link

IEEEXPLORE

XXIX Conference on Design of Circuits and Integrated Systems (DCIS 2014)

Title

FPGA Implemented Cut-Through vs Store-and-Forward Switches for Reliable Ethernet Networks

Abstract

In this paper, the latency times offered by two COTS IEC 62439-3 switch IP cores implementable on FPGAs have been compared. The first one, combines Cut-Through with Store-and-Forward switching architectures. The second IP is based only on Store-and-Forward switching technique. The analysis shows that a custom architecture that combines Cut-Through with Store-and-Forward approaches and takes advantage from Reconfigurable Technology offers the best latency times under any circumstance. This parameter is critical for the applications and sectors addressed in these new Reliable Ethernet protocols. Additionally, both IPs have been compared attending other features and resources required for their implementation. This comparison shows that a specifically designed architecture for the protocols specified in IEC 62439-3 offers excellent latency time and requires less resources than traditional Store-and-Forward ones.

39th Annual Conference of the IEEE Industrial Electronics Society

Title

SHA-3 based Message Authentication Codes to Secure IEEE 1588 Synchronization Systems

Abstract

Since the publication of IEEE 1588-2008 standard, the interest in giving cyber-security to Precision Time Protocol (PTP) traffic has increased. Therefore, several researches regarding security vulnerabilities and possible implementation improvements can be found in the literature. Particularly, SHA-1 and SHA-2 based MAC algorithms specified in the standard have already been proved to be suboptimal. In this paper, the utilization of new SHA-3 based MAC is proposed and both AES-128 and SHA-3 hardware implementations are compared in the context of PTP networks.

Link

IEEEXPLORE

Title

System-on-Chip Implementation of Reliable Ethernet Networks Nodes

Abstract

Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. However, the diversity and variety of emerging Ethernet based Industrial Protocols make difficult for the Industry the selection of the technology to implement them. Furthermore, the continue evolution of the standards and their combination increment the risk in the engineering decisions. This need for flexibility combined with the need for hardware processing make FPGAs and reconfigurable devices in general, the best candidates to implement network devices and equipments able to deal with these issues. In this work, 3 architectures for Reliable Network Devices that support HSR and PRP protocols are presented. These architectures benefit from cutting-edge 28nm silicon fabrication reconfigurable technology combined with on-chip ARM processors and peripheral. One of the proposed architectures is implemented following a Design Flow that integrates 3 complex EDA tools and a third-party IP to achieve a full operative Reliable Networking Device with HSR and PRP processing capabilities.

Link

IEEEXPLORE

Title

Memory Requirements Analysis for PRP and HSR Hardware Implementations on FPGAs

Abstract

The IEC62439-3 defines two ways to obtain a high availability automation network: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR). In order to do that, those methods include different paths to send information frames from source to destination and add a redundancy field to the frames. Nodes in the network must remember arrived frames so as to manage the duplicated information. In this paper the requirements of memory needed for a hardware implementation are analyzed.

Link

IEEEXPLORE

Title

Duplicate and Circulating Frames Discard Methods for PRP and HSR (IEC62439-3)

Abstract

Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defined in the IEC62439-3 about high availability automation networks and proposed as reference network topologies for substation communication networks by IEC61850, assure the upkeep of the communication when an error in a network occurs. Those methods consist in sending information duplicated through different and independent paths; so that nodes must be capable to eliminate the duplicated information circulating in the network. This paper analyzes ways to do the discard of those frames, which is crucial for a good implementation of the standard.

Link

IEEEXPLORE

 

September 2013

39th Annual Conference of the IEEE Industrial Electronics Society (IECON 2013)

Title

PRP and HSR Version 1 (IEC 62439-3 Ed.2), Improvements and a Prototype Implementation.

Abstract

The IEC62439-3: Industrial communication networks – High availability automation networks – Part 3: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defines two protocols which provides zero time recovery against a failure in the network. The first edition of the standard was published in 2010, and two years after a second edition has been published in July 2012. There have been some improvements which explain this actualization and an amendment between versions. This paper presents the most remarkable improvements included, others susceptible of being included and a software prototype to be run in PCs and/or FPGAs which implements this new version of the protocols.

Title

Memory Requirements Analysis for PRP and HSR Hardware Implementations on FPGAs.

Abstract

The IEC62439-3 defines two ways to obtain a high availability automation network: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR). In order to do that, those methods include different paths to send information frames from source to destination and add a redundancy field to the frames. Nodes in the network must remember arrived frames so as to manage the duplicated information. In this paper the requirements of memory needed for a hardware implementation are analyzed.

Title

Duplicate and Circulating Frames Discard Methods for PRP and HSR (IEC62439-3).

Abstract

Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defined in the IEC62439-3 about high availability automation networks and proposed as reference network topologies for substation communication networks by IEC61850, assure the upkeep of the communication when an error in a network occurs. Those methods consist in sending information duplicated through different and independent paths; so that nodes must be capable to eliminate the duplicated information circulating in the network. This paper analyzes ways to do the discard of those frames, which is crucial for a good implementation of the standard.

Title

High-availability Seamless Redundancy for Train Ethernet Consist Network.

Abstract

The Train Communication Network standard (TCN) have more than 10 year and now is evolving to the use of Ethernet. But there is necessary to adapt Ethernet to critical applications. In this sense, a new redundancy protocol, the High availability Seamless Redundancy (HSR) protocol can help to achieve the requirements. Most important features of the HSR are analyzed and the implementation of a HSR IP core module is presented.

System-on-Chip Implementation of Reliable Ethernet Networks Node.

Abstract

Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. However, the diversity and variety of emerging Ethernet based Industrial Protocols make difficult for the Industry the selection of the technology to implement them. Furthermore, the continue evolution of the standards and their combination increment the risk in the engineering decisions. This need for flexibility combined with the need for hardware processing make FPGAs and reconfigurable devices in general, the best candidates to implement network devices and equipments able to deal with these issues. In this work, 3 architectures for Reliable Network Devices that support HSR and PRP protocols are presented. These architectures benefit from cutting-edge 28nm silicon fabrication reconfigurable technology combined with on-chip ARM processors and peripheral. One of the proposed architectures is implemented following a Design Flow that integrates 3 complex EDA tools and a third-party IP to achieve a full operative Reliable Networking Device with HSR and PRP processing capabilities.

Title

SHA-3 based Message Authentication Codes to Secure IEEE 1588 Synchronization Systems.

Abstract

Since the publication of IEEE 1588-2008 standard, the interest of researchers in giving cyber-security to PTP traffic has increased and therefore, several articles regarding security vulnerabilities and possible implementation improvements can be found in the literature. Particularly, SHA-1 and SHA-2 based MAC algorithms specified in the standard have already been proved to be suboptimal. In this paper, the utilization of new SHA-3 based MAC is proposed and both AES-128 and SHA-3 hardware implementations are compared in the context of PTP networks.

 

22nd IEEE International Symposium on Industrial Electronics (ISIE). IEEE

Title

IEEE 1588 Transparent Clock Architecture for FPGA-based Network Devices.

Abstract

Apart from traditional test and measurement systems where clock synchronization is required, new emerging application areas like SmartGrids and 4G cellular mobile backhaul networks present strong timing constraints in terms of precise time synchronization. Precision Time Protocol (PTP), as defined in IEEE 1588 standard, offers sub-microsecond synchronization using conventional Ethernet networks. Thus, its acceptance is heavily increasing. However, the protocol performance was reduced in large cascaded networks with varying latencies. This drawback was later softened by the second version of the standard with the introduction of the Transparent Clock (TC) device. In this paper, a general overview of PTPv2 and the utilization of TCs is outlined. The main contribution is a new TC architecture for a FPGA-based network device that benefits from reconfigurable devices flexibility.

Link

IEEE

June 2013

A summary of the work named “Reliability Measurement of FPGA Implementations on Software-Designed Radio Platforms” presented at the SDR-WInnComm-Europe 2013 (Munich, Germany).

Reliability Measurement of FPGA Implementations

on Software-Defined Radio Platforms

Cutting-edge Software-Defined Radio Platforms for Tactical Radios are designed according strict standards to be functional on harsh environment. Good examples of these standards are VPX (VITA 46) and VPX REDI. These platforms, from the system- level point of view, are heterogeneous systems composed of GPUs, ASICs and FPGAs.

The Reliability Measurement of these systems is a concern, and research activity in this field is very active. On one hand, in order to ensure functionality in critical missions and on the other hand, to fulfill the requirements set in different certification standards. The platform vendor of final customer would need to address the safety and reliability requirements for the hardware and software implementations. For the hardware part, as an example, well known standards are DO-254 for Airborne systems, IEC 61508 for Safety-critical Systems or specific MIL certifications for Defense applications. For software part, the reliability is also covered by specific standards like DO-178.

In many of these cases, the platform vendor needs to offer a reliability measurement in terms of MTBF parameter or equivalent (as Lambda). These parameters are provided by the microelectronic circuit’s manufacturer for ASICs or GPUs devices. However, the reliability analysis of FPGA implemented designs is not seamless. Each design implemented on an FPGA has different layout inside the device and it require different number of resources and will be placed and routed using different internal locations. This leads to different behavior of the implementation against Single-Event Effects, the most important source of Faults on SRAM based FPGAs. Furthermore, the SRAM based FPGAs are gaining more and more importance on cutting-edge SDR platforms.

From the SDR point-of-view, these effects could lead to loose the communication link. For mission-critical systems, this risk must be quantified and mitigated up to a reasonable level. Thus, a lot of research effort is being developed to mitigate SEU effect and to ensure the requested reliability level of a given implementation on a FPGA.

This presentation focuses on a novel methodology valid to measure experimentally the reliability of design implementations on FPGAs. In the first Section, an introduction to the Reliability on Electronic devices will be addressed, focusing on reconfigurable devices. The next section summarizes the Fault Tolerance and Error Mitigation techniques that can be used to ruggedized FPGA implemented designs. In the third Section, a Methodology to Experimentally Measure the reliability of a given FPGA implementation is addressed and it is applied to two designs common on SDR applications.

The  first  analysis  presented  is  the  resilience  against  SEU  effects  of  Cryptography Cipher Blocks implemented on FPGAs. The robustness of AES, DES and TwoFish is measured and compared.

The second analysis is a study of the effect of different approaches of Triple Modular Redundancy applied to FPGA standard on-chip bus. For SDR designs implemented on FPGA, these on-chip interconnection means are critical. They are used to link the different Digital-Signal Processing and control modules involved in the design. Furthermore,  on-chip  interconnection  standards  are  playing  a  vital  role  on  the heterogeneous SDR implementations (GPUs, DSPs and FPGAS) and on standardization (CORBA hardware layers).

 The presentation also summarizes some COTS hardware that can be used to implement designs specifically protected against SEU effects.

The presentation ends with the conclusions and future work in this field.

Full presentation here:

Reliability Measurement of FPGA Implementations on Software-Designed Radio Platforms