SoC-e’s Managed Ethernet Switch (MES) IP core is a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements a Store & Forward switching approach that fulfills Ethernet standard policy regarding frame integrity checking. The switch buffers and verifies each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Consequently, MES is the perfect switch to implement Ethernet based Industrial Networks.
MES is a tri-speed (10/100/1000 Mpbs) switch IP and supports IEEE 1588 V2 Transparent Clock functionalities. This features modifies PTP event messages taking into account the time spent crossing the switch. This scheme improves distribution accuracy by compensating delivery variability across the network.
Furthermore, MES also supports IEEE 1588 V2 One Step Transparent Clock Peer-to-Peer (P2P) functionality by using independent hardware for each port. This feature allows compensating the residence time but also the delay of each link.
MES can be used in combination with SoC-e HSR-PRP Switch IP to introduce HSR and PRP capabilities in the ports that are required. HSR switching approach is Cut Through. Thus, the combination offers the maximum performance and maximum compatibility with the standards.
MES can be supported on Xilinx Spartan-6 and every 7-Series devices.
MES IP Core provides MII/GMII/RGMII native interface for Ethernet PHY devices and it can be combined with Xilinx IP to support SGMII among other interfaces.
Managed Ethernet Switch IP Core key features:
- Full-Duplex Ethernet 10/100/1000base-TX FX interfaces.
- Configurable 2 to 12 Ethernet ports.
- MII/GMII/RGMII interfaces for attaching to an external Physical Layer device (PHY).
- Possible to work with different data rate (10/100/1000base-tx fx Mbps) for each port.
- Automatic MAC addresses learning and aging (up to 2048 entries).
- Ethertype Based Switching.
- Switching Portmask: User-defined forwarding of frames to concrete ports.
- Port-based VLAN support.
- MDIO, UART, AXI4-lite or CoE (Configuration-over-ethernet) management interfaces.
- IEEE 1588v2 Stateless Transparent Clock functionality (P2P – Layer 2/ E2E – Layer 2).
- IEEE 802.1X EAPOL hardware processing.
- Priorities (PCP-802.1p, DSCP TOS, Ethertype)
- RSTP (Software stack required)
- Hardware support of RSTP.
- Reference RSTP stack for Linux provided with the IP Core.
- Posix Compatible RSTP stack available.
- MRP (Software stack not required)
- Ring Manager (MRM)
- Ring Client (MRC)
- Managed Ethernet Switch IP Core block diagram -
Supported boards for the Reference Designs:
- Featured boards:
- Other boards:
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