mrs

ManagedRedundantSwitch IP core (MRS) is a combination of SoCe HSR-PRPSwitch (HPS) and ManagedEthernetSwitch (MES) IP cores offering a redundant Ethernet switch capability. The MES module is a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements Store&Forward switching approach in order to ful l Ethernet standard policy regarding frame integrity checking each frame before forwarding them. On the other hand, the HPS module introduces HSR and PRP redundant capabilities in the ports that are required. HSR switching approach is Cut-Through.

Thus, the combination of MES and HPS offers the maximum performance and maximum compatibility with the standards.

MRS can be supported on the following Xilinx FPGA Families:

  • 6-Series (Spartan, Virtex)
  • 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
  • Ultrascale (Kintex, Virtex)
  • Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
MRS_17.05_Vivado_17.01

MRS is designed to be easily integrated in your FPGA designs by taking advantage of the new Xilinx Vivado Tool, that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.

Managed Redundant Switch IP Core key features:

  • Full-Duplex Ethernet 10/100/1000.
  • Half-Duplex Ethernet 10/100.
  • Configurable 3 to 16 Ethernet ports.
  • MII/GMII/RGMII interfaces for attaching to an external Physical Layer device (PHY).
  • Different data rate (10/100/1000 mbps) for each port.
  • Dynamic MAC Table with automatic MAC addresses learning and aging (up to 2048 entries).
  • Static MAC Table (up to 2048 entries).
  • Jumbo Frame Management.
  • Ethertype Based Switching.
  • Ingress Port Mirroring.
  • Broadcast Storm Protection.
  • Multicast Frame Filtering.
  • Switching Portmask: User-defined forwarding of frames to concrete ports.
  • Port-based VLAN support.
  • MDIO, UART, AXI4-lite or CoE (Configuration-over-ethernet) management interfaces.
  • IEEE 1588v2 Stateless Transparent Clock functionality (P2P – Layer 2/ E2E – Layer 2).
  • IEEE 802.1X EAPOL hardware processing.
  • QoS
    • Priorities (PCP-802.1p, DSCP TOS, Ethertype)
  • RSTP (Software stack required)
    • Hardware support for RSTP.
    • Reference RSTP stack for Linux provided with the IP Core.
    • Posix  Compatible RSTP stack available.
  • MRP (Software stack not required)
    • Ring Manager (MRM)
    • Ring Client (MRC)
  • DLR (Software stack not required)
    • Beacon Based Node
    • Supervisor Node
  • HSR
    • Supported HSR modes: H, N, T, U,X
  • PRP
    • Supported PRP modes: Duplicates Discard, Duplicates Accept
mrs_block_diagram
- Managed Redundant Switch IP Core block diagram -

Supported boards for the Reference Designs:

  • SoC-e SMARTzynq brick
  • For other Xilinx/Avnet/SoC-e boards, we can provide a time-limited IP Core for evaluation.

For more information, please contact us at: info@soc-e.com