Unmanaged Ethernet Switch IP Core

Full-crossbar IEEE 1588 Ethernet Switch in a single FPGA 

DSC_0791SoC-e’s Unmanaged Ethernet Switch IP core (UES) implements a plug-and-play Ethernet switch on reconfi gurable devices. It does not require external confi guration. It has been designed to address the maximum throughput using the minimum resources.

The switch implements a non-blocking crossbar matrix that allows wire-speed communication among all the ports. The switch buff ers and verifi es each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Furthermore, UES supports IEEE 1588 V2 Transparent Clock functionalities. This feature, that corrects PTP frames introducing the error generated by the switch, allows the interconnection of IEEE 1588 synchronized devices maintaining the highest levels of accuracy.

UES is the perfect Ethernet Switch IP to implement Ethernet based Industrial Networks.

UnmanagedEthernetSwitch IP Core Brochure

UES can be combined with our HSR-PRP Switch IP to introduce HSR and PRP capabilities in the required ports. HSR switching approach is Cut-Through. Thus the combination offers the maximum performance and maximum compatibility with the standards.

Unmanaged Ethernet Switch IP core key features:

  • Plug-and-Play: No con figuration required
  • High Performance: Full-crossbar matrix among ports implemented to allow maximum throughput
  • Fast: Very reduced Latency Times thanks to SoC-e proprietary MAC address matching mechanism
  • Efficient: Optimized to require few logic resources in order to allow the implementation on low-cost FPGA devices
  • Extensible: Zynq version available
  • Flexible: Fully scalable and confi gurable to obtain the best functionalities-size trade-off . The following parameters are available for the designer:
    • Number of ports
    • MAC address table length
    • Buffers queue length
    • IEEE Transparent Clock functionalities
  • Automatic: MAC addresses learning and aging (by default, store capacity of 256 MAC addresses).
  • Media Independent Interface (MII) for attaching to an external Physical Layer device (PHY). 100 Mbps Full-Duplex Ethernet interfaces (Evaluation Design).
  • Gigabit Media Independent Interface (GMII) for attaching to an external Physical Layer device (PHY). 1 Gpbs Full-Duplex Ethernet interfaces.
  • 1588 V2 Transparent Clock functionalities supported (not in the Evaluation Design).


- UnmanagedEthernet Switch IP Core block diagram -

Supported boards for the Reference Designs:

For more information, please contact us at: info@soc-e.com