clocks_rotated_400TSN stands for Time Sensitive Networking. It is the name of the IEEE 802.1 Task Group responsible for standards at Data Link Layer. This group provides the specifications that will allow time-synchronized, low latency, streaming services through IEEE 802 networks.

TSN is unique in that its streams are delivered with guaranteed bandwidth and deterministic latency. There are many features involved in the multiple standards currently under development. Some of the most relevant features and associated standards are:

  • Synchronization: The synchronization is based on IEEE 1588-2008 protocol. A specific profile is defined at IEEE 802.1AS.
  • Preemption: The concept of preemption is supported in TSN. A higher priority frame can interrupt the lower priority frame transmission in order to reduce the latency of time-sensitive streams (IEEE 802.1Qbu & IEEE 802.3br).
  • Traffic shaper: In order to achieve the theoretical lowest possible latency in engineered networks, the Time Aware Shaper functionality is introduced in TSN. This works with applications where time-critical data is sent on regular periodic intervals and it is based on adding time gates on each queue on a port.
  • Redundancy: The high-availability on TSN can be achieved by adding frame replication and elimination as defined in IEEE 802.1CB. In a similar way as defined for HSR, the frames include a sequence number and they are replicated. Each copy is sent through a different path in the network.

TSN is evolving and it is targeting different sectors, like Automotive, Industry, Broadcasting and Aerospace. Therefore, it is expected switching implementations that combine a subset of the available standards and features. This flexibility can be achieved through reconfigurable logic (FPGAs), HDL IPs and embedded software. Thus, programmable SoCs are perfect candidates for TSN implementations.

Time Sensitive Networking (TSN) Switch IP is a non-blocking switching matrix specifically designed to implement Ethernet TSN in Industrial and Aerospace equipment. It can be used as a base for a custom TSN configuration and it can be adapted to support a different subset of the standards.

TSN Switch IP Core provides MII/GMII/RGMII native interface for Ethernet PHY devices and it can be combined with Xilinx IP to support SGMII among other interfaces.

TSN Switch IP Core key features:

  • IEEE 802.1AS (IEEE 1588v2 P2P – Layer 2, 802.1AS profile).
  • Full-Duplex Ethernet 10/100/1000base-TX FX interfaces.
  • Configurable 2 to 12 Ethernet ports.
  • MII/GMII/RGMII interfaces for attaching to an external Physical Layer device (PHY).
  • Possible to work with different data rate (10/100/1000base-tx fx Mbps) for each port.
  • Automatic MAC addresses learning and aging (up to 2048 entries).
  • Ethertype Based Switching.
  • Switching Portmask: User-defined forwarding of frames to concrete ports.
  • Port-based VLAN support.
  • MDIO, UART, AXI4-lite or CoE (Configuration-over-Ethernet) management interfaces.
  • IEEE 802.1X EAPOL hardware processing.
  • Redundancy: P802.1CB (Standard in draft, technical development in process).
  • Frame preemption: P802.1Qbu (Standard in draft, technical development in process).
  • Schedule traffic: P802.1Qbv (Standard in draft, technical development in process).
  • Traffic policer to limit the excess traffic (the incoming data stream).(Standard in draft, technical development in process).
  • Traffic shaper to limit the transmit rate.(Standard in draft, technical development in process).

Supported boards for the Reference Designs:

For more information or to request early-access to the IEEE 802.AS design, please contact us at: