Time Sensitive Networking (TSN) offers an IEEE standard communication technology that enables interoperability between standard-conformant industrial devices from any vendor. It also eliminates the need for physical separation of critical and non-critical communication networks, which allows a direct exchange of data between operation centers and companies, a concept at the heart of the Industrial Internet of Things (IIoT). End-to-end TSN Network This article describes creating an end-to-end TSN network using specialized PCI Express (PCIe) cards and two final Linux endpoints.…
Running the Corporate Run of Bilbao 2022
The Corporate Run has been held in Bilbao and SoC-e has participated with a fabulous team of four colleagues: Igor, Jon, Mikel and Fran. More than a thousand athletes have run the 8 kilometers that started from the Euskalduna palace. The aim of the Corporate Run is to combine sport, healthy living, fun and friendship around Bilbao. To be a meeting point for all colleagues looking to take part in a different event where competitiveness takes a back seat. In…
Testing & Verifying complex FPGA designs – Part III
Simulation & Verification are fundamental in the process of developing any good quality FPGA-based RTL codification. These are key steps within SoC-e’s designing procedures, and in this article, we are going to provide more insights about them in our Networking IP Core portfolio. The whole process is divided into the following high-level steps: Entity/Block-oriented simulation: Simulation at entity/block-level for the different modules that compose each IP Core, by generating stimulus on each input signal and verifying that the RTL code…
Webinar: HSR, PRP & PTP for IEC 61850 Digital Substations
From IP Cores up-to Added Value Equipment for Substation Automation SoC-e will be presenting a new webinar in collaboration with its Indian distributor, ESS. In this session, attendees will have the opportunity to learn more about HSR & PRP protocols and their convenience for electrical substation automation and mission-critical application that cannot tolerate any system downtime. SoC-e products will also be introduced, starting from the technology approach (HSR/PRP Switch IP Core) up to COTS solutions. In particular, we will be…
SoC-e taking part in the first 2022 TSN Testbed of IIC
As in previous years, the Industrial Internet Consortium (IIC) has organized a Time Sensitive Networking (TSN) related testbed, which is now taking place in Stuttgart, Germany, from April 26th (Tuesday) until Thursday 28th (Thursday). After a complicated 2020 and 2021, in which most of the actions have been virtual due to the pandemic, seems that we are gradually returning to normality. We didn’t want to miss the opportunity, so SoC-e team already travelled in order to attend the event. More…
SoC-e in the CSW Spring 2022 (HiPEAC): Research on Automotive In-Vehicle Network SoC Technologies
HiPEAC is a European network of almost 2,000 world-class computing systems researchers, industry representatives and students. It is a platform for research collaboration that promotes the transformation of research into new products or services among other goals. Starting tomorrow (26th April) and until the 28th of April, HiPEAC will organize the Computing Systems Week in Tampere (Finland). On this occasion, SoC-e will be participating in the following keynote: Research on Automotive In-Vehicle Network SoC Technologies for Next-Generation Zonal Gateway Controllers.…
Testing & Verifying complex FPGA designs – Part II
Simulation & Verification are fundamental in the process of developing any good quality FPGA-based RTL codification. These are key steps within SoC-e’s designing procedures, and in this article, we are going to provide more insights about them in our Networking IP Core portfolio. The whole process is divided in the following high-level steps: Entity/Block-oriented simulation: Simulation at entity/block-level for the different modules that compose each IP Core, by generating stimulus on each input signal and verifying that the RTL code…
Latency comparison between Cut-Through and Store-and-Forward FPGA implemented switching IP
In this article a comparison in latencies of two COTS IEC 62439-3 switch IP cores implementable on FPGAs is shown. The first one, combines Cut-Through with Store-and-Forward switching architectures, and the second one is based only on Store-and-Forward switching technique. Reliable Ethernet Networks – HSR & PRP Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. One illustrative example of this evolution, is the adoption by the International Electrotechnical Commission of the High-availability Seamless Redundancy (HSR) Ethernet based…
Testing & Verifying complex FPGA designs – Part I
Simulation & Verification are fundamental in the process of developing any good quality FPGA-based RTL codification. These are key steps within SoC-e’s designing procedures, and in this article, we are going to provide more insights about them in our Networking IP Core portfolio. The whole process is divided in the following high-level steps: Entity/Block-oriented simulation: Simulation at entity/block-level for the different modules that compose each IP Core, by generating stimulus on each input signal and verifying that the RTL code…
SoC-e in the COMMUTE project
We have recently participated in the Hazitek grant programme! As SoC-e is a company fully committed to R&D, the Basque Government has recently awarded us a grant for the COMMUTE project: design and development of a high-performance, cybersecure, application-oriented and reconfigurable Ethernet communications platform. Ethernet-based communications in the office environment (Information Technologies-IT) are widely known and mature. The global digitalization process that the Industrial, Energy, Transport and Aerospace sectors are undergoing is generating demand for Ethernet solutions for IT and…