IRIGtimeM: IRIG-B Master IP core

The term IRIG signals is  used to refer to a whole group of serial timecodes, which use a continuous stream of binary data to transmit information on date and time. The individual time code formats can be distinguished by the signal characteristics, e.g. modulated versus unmodulated, which require different ways of signal transmission, by the data rate, and by the kind of information included in the transmitted data.

Back in 1956 the TeleCommunication Working Group (TCWG) of the American Inter Range Instrumentation Group (IRIG) was mandated to standardize different time code formats, resulting in IRIG Document 104-60. The latest revision is IRIG Standard 200-04 which is the current version specifying some new codes which also transmit a year number. IRIGB is widely used to synchronize systems in Substation Automation Systems (SAS) and in Defence and Aerospace. Nowadays, it is quite frequent combining IEEE 1588 systems with IRGIB systems. The following diagram maps as an example the functionalities of SoC-e timing related IPs of SAS equipment related to synchronization.


IRIGtimeM implements an IRIG 200-04 compliant time synchronization master on FPGA devices. This IRIG-B master IP has been designed to support all the IRIG-B coded expressions as well as DCLS and AM modulations in order to provide maximum flexibility.



This IRIG-B master IP generates IRIG-B frames each second, including the mandatory and optional time information (seconds, minutes, hours, days, years, control functions and binary straight seconds) depending on the IRIG-B time code selected on the confi guration. This IP has been designed to provide autonomous operation, requiring as less con figuration as possible. The standard features included in IRIGtimeM IP core are:


  •  IRIG 200-04 compliant time synchronization master
  •  Support for DCLS and AM modulations
  •  Support for all IRIG-B coded expressions, including year information, control functions and
    straight binary seconds
  • Output type (IRIG-B timecode) con figurable both before implementation and on
    the fly
  • Precise IRIG-B output in order to provide nanoseconds precision
  • 32-bit timestamp input for initial set up of the IP
  • Periodic pulse output for testing
IRIGtimeM IP core block diagram is represented in the following figure:
IRIGtimeM IP core block is supported in several Xilinx FPGA families. As a reference, these are the resources needed on the smaller Spartan-6 fpga (LX9)
  • 625 Slices
  • 868 Slice Registers
  • 1840 LUTs
  • 7 RAMB16BWER memory block
  • 4 DSP48A block
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