IRIGtimeS: IRIG-B Slave IP core

The term IRIG signals is  used to refer to a whole group of serial timecodes, which use a continuous stream of binary data to transmit information on date and time. The individual time code formats can be distinguished by the signal characteristics, e.g. modulated versus unmodulated, which require different ways of signal transmission, by the data rate, and by the kind of information included in the transmitted data.

Back in 1956 the TeleCommunication Working Group (TCWG) of the American Inter Range Instrumentation Group (IRIG) was mandated to standardize different time code formats, resulting in IRIG Document 104-60. The latest revision is IRIG Standard 200-04 which is the current version specifying some new codes which also transmit a year number. IRIGB is widely used to synchronize systems in Substation Automation Systems (SAS) and in Defence and Aerospace. Nowadays, it is quite frequent combining IEEE 1588 systems with IRGIB systems. The following diagram maps as an example the functionalities of SoC-e timing related IPs of SAS equipment related to synchronization.


IRIGtimeS implements an IRIG 200-04 compliant time synchronization slave on FPGA devices. This IRIG-B slave IP has been designed to support all the IRIG-B coded expressions as well as DCLS and AM modulations in order to provide maximum flexibility.



This IRIG-B slave IP receives IRIG-B frames each second, getting the time information (seconds, minutes, hours, days, years, control functions and binary straight seconds) depending on the IRIG-B time code. This IP implements a 64-bit internal timer in order to provide the timestamp (in seconds) and nanoseconds value. This timer is synchronized in value and frequency with the received IRIG-B time information. This IP has been designed to provide autonomous operation, requiring as less con figuration as possible. The standard features included in IRIGtimeS IP core are:


  •  IRIG 200-04 compliant time synchronization slave
  •  Support for DCLS and AM modulations
  •  Support for all IRIG-B coded expressions, including year information, control functions and
    straight binary seconds
  • Sub-microsecond synchronization with the IRIG-B master
  • 64-bit internal timer synchronized in time and frequency with the IRIG-B master
  • 32-bit for timestamp in seconds and 32-bit for nanoseconds
  • Periodic pulse output for testing
IRIGtimeS IP core block diagram is represented in the following figure:
IRIGtimeS IP core block is supported in several Xilinx FPGA families. As a reference, these are the resources needed on the smaller Spartan-6 fpga (LX9)
  • 634 Slices
  • 1409 Slice Registers
  • 1929 LUTs
  • 5 DSP48A blocks
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