HSR-PRP Switch IP Core


All hardware low-latency switch for FPGAs

HSR / PRP Switch

HSR-PRP Switch is an IP Core for the implementation of High-availability Seamless Redundancy and Parallel Redundancy Protocol (HSR and PRP, IEC 62439-3-Clause 5 and 4 respectively) protocols for Reliable Ethernet communications. HSR-PRP Switch is a full hardware solution that can be implemented on a low-cost FPGA.

HSR/PRP Switch IP Core Brochure

It is a flexible solution for the Energy Market Equipments that will be connected to HSR rings, PRP Lans or will work as Network bridges in the context of IEC 61850.

HSR-PRP Switch IP core key features:

  • Fast Ethernet (100Mb) and Gigabit (1GB) versions available
  • It switches frames by hardware. This feature offers high switching speeds, needed to fulfill the Maximum Allowed Age and Data Integrity set for Process Bus and Inter-bay Bus in Electric Substation Automation
  • The processing architecture has been designed specifically for HSR/PRP. Forwarding latencies in range of 500ns for Gigabit Ethernet
  • It is an all-hardware. There is no need for on-chip microprocessor nor software stack
  • It has been optimized to require few logic resources in order to allow the implementation on low-cost FPGA devices
  • It supports IEEE 1588-2008 V2 combined with SoC-e 1588 IP cores
  • It can be used to implement End-Node DAN, RedBox or QuadBox functionalities
  • It has been provided with a single flag that switches between PRP and HSR modes
  • It includes complete statistics and error registers for each port integrated (Network Supervision)
  • Supported HSR modes: H, N, T, U
  • Supported PRP modes: Duplicates Discard, Duplicates Accept
  • VLAN support and HSR Rings id
  • Evaluation Designs for Spartan-6 and Zynq devices
  • SMNP and MIB Table available
  • Configuration-over-Ethernet (COE): Full access to internal registers through the same Ethernet link that connects to the CPU
  • Dynamic Bitstream Configuration: Allows changing remotely the functionality of the FPGA

HSR-PRP Switch IP core customizable features for optimum resources/functionalities trade off:

  • Node Table size
  • Forwarding Queues size independent for each port
  • 1588 Transparent Clock in Redundant and Interlink Ports
  • Scalable duplicate/circulate discard table
  • VLAN Priority support
  • Access to internal registers via MDIO or UART
  • RedBox mode with integrated SAN proxy
  • 1588 Hybrid Clock

 HSR_PRP

- Non Redunant Network VS Zero Switch-Over Reliable Network -

Supported boards for the Reference Designs:

Features implemented on the Reference Designs:

  • Standard version of HSR-PRP Switch implements RedBox topology
  • Two ports (Port A and Port B) implement Dual Attached Node (DAN) capability
  • The remaining port (Port C) offers a conventional Ethernet link to any on-board or external CPU with integrated SAN proxy
  • Zynq Reference Design implements a full DAN using Internal Link to ARM9 Processor and Linux

Access

Location   FTP

HSR/PRP Virtual Image for PC

HSR/PRP Switch IP core Evalution Version