Managed Ethernet Switch (MES) IP core features a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements a Store & Forward switching approach that fulfills Ethernet standard policy regarding frame integrity checking. The switch buffers and verifies each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Consequently, MES is the perfect switch to implement Ethernet based Industrial Networks.
MES is a tri-speed (10/100/1000 Mpbs) switch IP and supports IEEE 1588 V2 Transparent Clock functionalities. This features modifies PTP event messages taking into account the time spent crossing the switch. This scheme improves distribution accuracy by compensating delivery variability across the network.
Furthermore, MES also supports IEEE 1588 V2 One Step Transparent Clock Peer-to-Peer (P2P) functionality by using independent hardware for each port. This feature allows compensating the residence time but also the delay of each link.
MES can be used in combination with SoC-e HSR-PRP Switch IP to introduce HSR and PRP capabilities in the ports that are required. HSR switching approach is Cut Through. Thus, the combination offers the maximum performance and maximum compatibility with the standards. It provides MII/GMII/RGMII native interfaces for Ethernet PHY devices and it can be combined with Xilinx IP to support RMII or SGMII among other interfaces. It also supports and AXI4-Stream interface to be connected to other IP Cores that do not feature MAC based interfaces.
MES can be supported on the following Xilinx FPGA Families:
- 6-Series (Spartan, Virtex)
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
- Managed Ethernet Switch IP Core for Xilinx Vivado Tool -
MES is designed to be easily integrated in your FPGA designs by taking advantage of the new Xilinx Vivado Tool, that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.
Managed Ethernet Switch IP Core key features:
- Full-Duplex Ethernet 10/100/1000.
- Half-Duplex Ethernet 10/100.
- Configurable 3 to 16 Ethernet ports.
- MII/GMII/RGMII interfaces for attaching to an external Physical Layer device (PHY).
- Different data rate (10/100/1000 mbps) for each port.
- Dynamic MAC Table with automatic MAC addresses learning and aging (up to 2048 entries).
- Static MAC Table (up to 2048 entries).
- Jumbo Frame Management.
- Ethertype Based Switching.
- Ingress Port Mirroring.
- Broadcast Storm Protection.
- Multicast Frame Filtering.
- Switching Portmask: User-defined forwarding of frames to concrete ports.
- Port-based VLAN support.
- MDIO, UART, AXI4-lite or CoE (Configuration-over-ethernet) management interfaces.
- IEEE 1588v2 Stateless Transparent Clock functionality (P2P – Layer 2/ E2E – Layer 2).
- IEEE 802.1X EAPOL hardware processing.
- Priorities (PCP-802.1p, DSCP TOS, Ethertype)
- RSTP (Software stack required)
- Hardware support for RSTP.
- Reference RSTP stack for Linux provided with the IP Core.
- Posix Compatible RSTP stack available.
- MRP (Software stack not required)
- Ring Manager (MRM)
- Ring Client (MRC)
- DLR (Software stack not required)
- Beacon Based Node
- Supervisor Node
- TSN (Time Sensitive Networking)
- IEEE 802.1AS (IEEE 1588v2 P2P – Layer 2, 802.1AS profile).
- Schedule traffic: 802.1Qbv (Standard in draft, technical development in process).
- Frame preemption: P802.1Qbu (Standard in draft, technical development in process).
- Managed Ethernet Switch IP Core block diagram -
Supported boards for the Reference Designs:
- SoC-e SMARTzynq brick (Recommended)
- For other Xilinx/Avnet/SoC-e/ boards, we can provide a time-limited IP Core for evaluation.
For more information, please contact us at: email@example.com