Unmanaged Ethernet Switch IP core (UES) implements a plug-and-play Ethernet switch on reconfigurable devices. It does not require external configuration. It has been designed to address the maximum throughput using the minimum resources.
The switch implements a non-blocking crossbar matrix that allows wire-speed communication among all the ports. The switch buffers and verifies each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Furthermore, UES supports IEEE 1588 V2 Transparent Clock functionalities. This feature, that corrects PTP frames introducing the error generated by the switch, allows the interconnection of IEEE 1588 synchronized devices maintaining the highest levels of accuracy.
UES is the perfect Ethernet Switch IP to implement Ethernet based Industrial Networks. It provides MII/GMII/RGMII native interfaces for Ethernet PHY devices and it can be combined with Xilinx IP to support RMII or SGMII among other interfaces. It also supports and AXI4-Stream interface to be connected to other IP Cores that do not feature MAC based interfaces.
UES can be supported on the following Xilinx FPGA Families:
- 6-Series (Spartan, Virtex)
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
- Unmanaged Ethernet Switch IP Core for Xilinx Vivado Tool -
UES is designed to be easily integrated in your FPGA designs by taking advantage of the new Xilinx Vivado Tool, that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.
Unmanaged Ethernet Switch IP core key features:
- Plug-and-Play: No configuration required
- High Performance: Full-crossbar matrix among ports implemented to allow maximum throughput
- Fast: Very reduced Latency Times thanks to SoC-e proprietary MAC address matching mechanism
- Efficient: Optimized to require few logic resources in order to allow the implementation on low-cost FPGA devices
- Flexible: Fully scalable and configurable to obtain the best functionalities-size trade-off. The following parameters are available for the designer:
- Number of ports: Configurable 3 to 16 Ethernet ports
- Buffers queue length
- IEEE Transparent Clock functionalities
- Automatic: MAC addresses learning and aging (by default, store capacity of 2048 MAC addresses).
- UnmanagedEthernet Switch IP Core block diagram -
MES is designed to be easily integrated in your FPGA designs by taking advantage of the new Xilinx Vivado Tool, that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.
Supported boards for the Reference Designs:
- SoC-e SMARTzynq brick (Recommended)
- For other Xilinx/Avnet/SoC-e/ boards, we can provide a time-limited IP Core for evaluation.
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