SocTek IP Cores is SOC-E’s product line focused on technology provider in the form factor of IP Cores for FPGA platforms.
This product line incorporates best-in-class, high-quality IP solutions that are specifically focused on critical applications, where nor even a single communication failure is allowed.
Our IP portfolio is divided into the following main technology categories:
Large set of user-configurable parameters (both at synthesis time and runtime) available that allow adapting its configuration & FPGA resource usage to the specific use case & programable platform available.
Non captive solutions that guarantee interoperability with other vendors
In order to adapt the COTS IP Core products to specific customer needs or use case.
IP updates & upgrades are periodically available so that they are aligned with the latest version of the standards. New features are introduced without the need to perform changes in the hardware (thanks to the reconfigurable FPGA & SoPC platforms) and making customer product robust against obsolescence.
Rigorously tested, hardware-validated and verified in real-life environments.
Software components (drivers & configuration API), documentation and example RTL design available for a faster IP Core integration and product time to market.
AMD/Xilinx and Microchip supported. Other vendors to be supported in the future.
Either by purchasing ready-to-use evaluation kits or by accessing to a time-limited, evaluation version of the IP Cores.
Functionality Hardware-only (VHDL) PTP slave clock
Communication Interfaces MII, GMII, RGMII or *Serialized (SGMII, QSGMII, etc…)
Port Speed 10M/100M/1G
Synchronization Multi-PTP profile capable (Layer-2/Layer-3, E2E/P2P, etc..), submicrosecond (below +/-1 us) offset from master
Outputs ToD PTP clock, PPS
Other Features Event timestamping, Alarm detection, Optional IRIG-B master output
Functionality PTP ordinary (master / time transmitter & slave / time receiver) clock
Communication Interfaces MII, GMII, RGMII or *Serialized (SGMII, QSGMII, etc…)
Port Speed 10M/100M/1G
Synchronization Multi-PTP profile capable (Layer-2/Layer-3, E2E/P2P, etc..), submicrosecond (below +/-100ns) offset from master
OutputsToD PTP clock, PPS, frequency selectable pulse output
Other FeaturesEvent timestamping , Alarm detection
Other Features Event timestamping, Alarm detection
Functionality IRIG 200-04 compliant master
Synchronization DCLS modulation
Inputs PPS and 10MHz reference
Other Features IEEE1344 extension supported, IRIG-B time codes configurable before implementation and on the fly
Functionality IRIG 200-04 compliant slave
Synchronization DLCS modulation, submicrosecond offset from master
InputsPPS and 10MHz reference
Other Features IEEE1344 extension supported, IRIG-B time codes configurable before implementation and on the fly
Functionality TSN EndPoint
Communication Interfaces MII, GMII, RGMII or *Serialized (SGMII, QSGMII, etc…)
Port Speed 100M/1G/10G
Synchronization IEEE 802.1AS, IEEE1588 (PTPv2)
Time-Sensitive Networking IEEE 802.1Qav, IEEE 802.1Qbv, IEEE 802.1Qci, IEEE 802.1CB, IEEE 802.1Qcc
Other FeaturesQoS, IEEE 802.1Q tag-based and Port-based VLANs
Functionality TSN Ethernet Switch
Communication Interfaces RMII, MII, GMII, RGMII or *Serialized (SGMII, QSGMII, etc…)
Port Speed 10M/100M/1G
Synchronization IEEE 802.1AS, IEEE1588 (PTPv2)
Time-Sensitive Networking IEEE 802.1Qav, IEEE 802.1Qbv, IEEE 802.1Qci, IEEE 802.1CB, IEEE 802.1Qbu / IEEE 802.3br, IEEE 802.1Qcc
Other FeaturesQoS, IEEE 802.1Q tag-based and Port-based VLANs, Spanning-Tree protocol, IEEE802.1X
Functionality TSN Ethernet Switch
Communication Interfaces RMII, MII, GMII, RGMII or *Serialized (SGMII, QSGMII, etc…)
Port Speed 10M/100M/1G
Synchronization IEEE 802.1AS, IEEE1588 (PTPv2)
Time-Sensitive Networking IEEE 802.1Qav, IEEE 802.1Qbv, IEEE 802.1Qci, IEEE 802.1CB, IEEE 802.1Qbu / IEEE 802.3br, IEEE 802.1Qcc
Other FeaturesQoS, IEEE 802.1Q tag-based and Port-based VLANs, Spanning-Tree protocol, IEEE802.1X
Functionality HSR/PRP redundancy
Communication Interfaces RMII, MII, GMII, RGMII or *Serialized (SGMII, QSGMII, etc…)
Port Speed 10M/100M/1G
Synchronization Stateless Transparent Clock (SLTC) with P2P delay mechanism
Redundancy HSR and PRP in multiple operation modes
Other FeaturesQoS, QuadBox-ready, cut-through in ring ports (HSR), MAC filtering
Functionality Managed Ethernet Switch
Communication Interfaces RMII, MII, GMII, RGMII or *Serialized (SGMII, QSGMII, etc…)
Port Speed 10M/100M/1G
Synchronization IEEE 802.1AS, IEEE1588 (PTPv2)
Redundancy Device Level Ring (DLR), Media Redundancy Protocol (MRP)
Other FeaturesQoS, IEEE 802.1Q tag-based and Port-based VLANs, Spanning-Tree protocol, IEEE802.1X
Functionality HSR/PRP redundancy + Legacy ethernet ports
Communication Interfaces RMII, MII, GMII, RGMII or *Serialized (SGMII, QSGMII, etc…)
Port Speed 10M/100M/1G
Synchronization Stateless Transparent Clock (SLTC) with P2P delay mechanism
Redundancy HSR, PRP, DLR and MRP
Other FeaturesQoS, IEEE 802.1Q tag-based and Port-based VLANs, Spanning-Tree protocol, IEEE802.1X, cut-through in ring ports (HSR)
FunctionalityVHDL automated testbench for SOC-E networking IP Cores
Test PlansPre-defined test plan & User-defined tests
IP Core CompatibilityETSN, MTSN, TGES, HPS, MES, MRS
EDA Tool CompatibilityAMD Vivado™ Design Suite & Aldec Riviera-PRO™ (recommended) and more
Functionality SpaceWire node
Communication Interfaces SpaceWire (external), AXI-Stream (internal)
Port Speed (up-to) 200Mbps
Other Features Designed to be compliant with ECSS-E-ST-50-12C, AXI4-Lite management interface with statistic registers