Deterministic Ethernet solutions, like TSN, deliver streams with guaranteed bandwidth and deterministic latency.

Time Sensitive Networking (TSN) is the name of the IEEE 802.1 Task Group responsible for standards at Data Link Layer. This group provides the specifications that will allow time-synchronized and low latency streaming services through IEEE 802 networks.

This new 10G TSN Ethernet Switch IP Core from SoC-e, is the evolution of the MTSN Switch IP Core. It is also a flexible HDL code ready to generate TSN endpoints or TSN bridge implementations, but with the option of having 10G ports. As with the other SoC-e IP Cores, this IP has a rich set of Generic parameters, in order to obtain the best functionalities resources trade-off. These generics can be configures graphically through the Vivado GUI as well.

10G TSN Ethernet Switch IP Core key features


  • Full-duplex 100M/1G/2.5G/5G/10G Ethernet Interfaces
  • Configurable up-to 32 Ethernet ports
  • MII/RMII/GMII/RGMII/SGMII/QSGMII/USXGMII Physical Layer device (PHY) interfaces. (For others, please contact us)
  • Different data rate supported for each port


  • Dynamic MAC Table with automatic MAC addresses learning and aging
  • Static MAC Table
  • Jumbo Frame Management
  • Broadcast/Multicast Storm Protection
  • Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)
  • Port-based VLAN support

Low Level Configuration

  • MDIO, UART or AXI4-lite management interfaces
  • Drivers are provided with IP Core purchase

Time-Sensitive Networking

  • IEEE 802.1AS for Time Synchronization Layer
  • IEEE 802.1Qav for Reserved Traffic
    • Credit Based Shaper: Configurable bandwidth reservation for each traffic class
  • IEEE 802.1Qbv for Scheduled Traffic
    • Time Aware Shaper: Configurable number of time slots
  • IEEE 802.1Qcc for Network Management
    • NETCONF for managing YANG data
  • IEEE 802.1Qci for Stream Filtering and Policing (*)
  • IEEE 802.1AB for LLDP (Link Layer Discovery Protocol)
  • IEEE 802.1w for Rapid Spanning Tree Protocol
  • IEEE 802.1s for Multiple Spanning Tree Protocol
  • IEEE 802.1CB for Frame Replication and Elimination for Reliability (*)
  • IEEE 802.1Qbu/802.3br for Frame Preemption (*)

High Level Configuration

  • NETCONF YANG model support (CNC configuration)
  • High-level Configuration GUI

*: Future Release and/or Interoperability Test pending.

Supported Xilinx FPGA Families and Evaluation boards

SoC-e 10G TSN Ethernet Switch IP Core can be deployed in the following Xilinx families. You can find the different Xilinx product tables and selection guides at the following links:

When it comes to Evaluation boards, SoC-e also develops System-on-Modules (SoMs) that can be provided with a preloaded design of SoC-e’s IP Cores. SoC-e can offer SoMs based on 7-Series, Ultrascale or Ultrascale+ Xilinx FPGA Families.

For other Xilinx/Avnet/SoC-e/ boards, SoC-e can provide a time-limited IP Core for evaluation.