Deterministic Ethernet solutions, like TSN, deliver streams with guaranteed bandwidth and deterministic latency. 

Time Sensitive Networking (TSN) is the name of the IEEE 802.1 Task Group responsible for standards at Data Link Layer. This group provides the specifications that will allow time-synchronized and low latency streaming services through IEEE 802 networks.

TSN is evolving and it is targeting different sectors, like Automotive, Industry, Broadcasting and Aerospace. Therefore, it is expected switching implementations that combine a subset of the available standards and features. This flexibility can be achieved through reconfigurable logic (FPGAs), HDL IPs and embedded software.

Multiport Time Sensitive Networking (MTSN) Switch IP core is a flexible HDL code ready to generate TSN end-point or bridge implementations. The IP has been provided with a rich set of Generic parameters to obtain the best functionalities resources trade-off. These generic can be configured at VHDL level or graphically thanks to the GUI interface provided for Vivado IPI. 

MTSN is supported on the following Xilinx FPGA Families:

  • 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
  • Ultrascale (Kintex, Virtex)
  • Ultrascale+ (Zynq MPSoC, Kintex, Virtex)

MTSN Switch IP Core key features:

Interfaces

  • Full-duplex 10/100/1000 Mbps Ethernet Interfaces
  • Configurable up-to 32 Ethernet ports
  • MII/RMII/GMII/RGMII/SGMII/QSGMII Physical Layer device (PHY) interfaces
  • Different data rate supported for each port

Switching

  • Dynamic MAC Table with automatic MAC addresses learning and aging
  • Static MAC Table
  • Jumbo Frame Management
  • Broadcast/Multicast Storm Protection
  • Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)
  • Port-based VLAN support

Time-Sensitive Networking

  • IEEE 802.1AS for Time Synchronization Layer
  • IEEE 802.1Qav for Reserved Traffic
    • Credit Based Shaper: Configurable bandwidth reservation for each traffic class
  • IEEE 802.1Qbv for Scheduled Traffic
    • Time Aware Shaper: Configurable number of time slots
  • IEEE 802.1Qcc for Network Management
    • NETCONF for managing YANG data
  • IEEE 802.1Qci for Stream Filtering and Policing
  • IEEE 802.1AB for LLDP (Link Layer Discovery Protocol)
  • IEEE 802.1w for Rapid Spanning Tree Protocol
  • IEEE 802.1s for Multiple Spanning Tree Protocol
  • IEEE 802.1CB for Frame Replication and Elimination for Reliability
  • IEEE 802.1Qbu/802.3br for Frame Preemption (*)
  • Cut-Through support for Isochronous Scheduled Traffic (*)

Low Level Configuration

  • MDIO, UART, AXI4-lite or CoE management interfaces
  • Configuration-over-Ethernet (CoE): Full access to internal registers through the same Ethernet link that connects to the CPU
  • Drivers are provided with IP Core purchase

High Level Configuration

  • RESTCONF/NETCONF YANG model support (CNC configuration)
  • High-level Configuration GUI

*: Future Release and/or Interoperability Test pending.

Supported boards for the Reference Designs:

Additional Information:

About Us

System-on-Chip engineering (SoCe) is a worldwide leading supplier of time-aware Ethernet networking solutions. SoCe is pioneer in developing a portfolio of IP cores and rugged platforms that implement these technologies for critical systems.

For more information, please contact us at: info@soc-e.com