IRIGtimeM implements an IRIG 200-04 compliant time synchronization master on FPGA devices. This IRIG-B master IP has been designed to support all the IRIG-B coded expressions as well as DCLS and AM modulations in order to provide maximum flexibility.
IRIGtimeM is supported on the following Xilinx FPGA Families:
- Managed Ethernet Switch IP Core for Xilinx Vivado Tool -
It is designed to be easily integrated in your FPGA designs by taking advantage of the new Xilinx Vivado Tool, that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.
- IRIG 200-04 compliant time synchronization master
- Support for DCLS and AM modulations
- Support for all IRIG-B coded expressions, including year information, control functions and straight binary seconds
- Output type (IRIG-B timecode) configurable both before implementation and on the fly
- Precise IRIG-B output in order to provide nanoseconds precision
- 32-bit timestamp input for initial set up of the IP
- Periodic pulse output for testing
Supported boards for the Reference Designs:
- SoC-e SMARTzynq brick (Recommended)
- For other Xilinx/Avnet/SoC-e boards, we can provide a time-limited IP Core for evaluation.