10G UES

10G Unmanaged Ethernet Switch IP core (10G UES) is an evolution of our 1G Unmanaged Ethernet Switch IP Core (UES). The 10G UES implements a plug-and-play Ethernet switch for reconfi gurable devices. It does not require external confi guration and it has been designed to address the maximum throughput using the minimum resources.

The 10G Unmanaged switch IP implements a non-blocking crossbar matrix that allows wire-speed communication among all the ports. The IP Core buffers and verifi es each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Furthermore, the switch IP Core supports IEEE 1588 V2 Transparent Clock functionalities. This feature, corrects PTP frames introducing the error generated by the switch, allows the interconnection of IEEE 1588 synchronized devices maintaining the highest levels of accuracy.

10G Unmanaged Switch IP Core is the perfect Ethernet Switch IP to implement Ethernet based Industrial Networks. It provides MII/GMII/RGMII native interfaces for Ethernet PHY devices and it can be combined with Xilinx Ethernet 1G/2.5G BASE-X PCS/PMA, it can support RMII or SGMII among other interfaces. It also supports and AXI4-Stream interface to be connected to other IP Cores that do not feature MAC based interfaces.

10G Unmanaged Switch can be supported on the following Xilinx FPGA Families:

  • 6-Series (Spartan, Virtex)
  • 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
  • Ultrascale (Kintex, Virtex)
  • Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
10G UES- 10G Unmanaged Ethernet Switch IP Core for Xilinx Vivado Tool -

10G Unmanaged Ethernet Switch IP core key features:

  • Plug-and-Play: No con figuration required
  • High Performance: Full-crossbar matrix among ports implemented to allow maximum throughput
  • Fast: Very reduced Latency Times thanks to SoC-e proprietary MAC address matching mechanism
  • Efficient: Optimized to require few logic resources in order to allow the implementation on low-cost FPGA devices
  • Flexible: Fully scalable and confi gurable to obtain the best functionalities-size trade-off. The following parameters are available for the designer:
    • Number of ports: Configurable 3 to 32 Ethernet ports
    • Port data rates: each port can be configured with differents speeds: 10/100/1000 Mbps and 2,5/5/10G
    • Buffers queue length
    • IEEE Transparent Clock functionalities
  • Automatic: MAC addresses learning and aging.

Supported boards for Reference Designs

  • SoC-e SMARTzynq brick (Recommended)
  • For other Xilinx/Avnet/SoC-e/ boards, we can provide a time-limited IP Core for evaluation.