Managed Ethernet Switch (MES) IP core features a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements a Store & Forward switching approach that fulfills Ethernet standard policy regarding frame integrity checking. The switch buffers and verifies each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Consequently, MES is the perfect switch to implement Ethernet based Industrial Networks.

MES is a tri-speed (10/100/1000 Mpbs) switch IP and supports IEEE 1588 V2 Transparent Clock functionalities. This features modifies PTP event messages taking into account the time spent crossing the switch. This scheme improves distribution accuracy by compensating delivery variability across the network.

Furthermore, MES also supports IEEE 1588 V2 One Step Transparent Clock Peer-to-Peer (P2P) functionality by using independent hardware for each port. This feature allows compensating the residence time but also the delay of each link.

MES can be used in combination with SoC-e HSR-PRP Switch IP to introduce HSR and PRP capabilities in the ports that are required. HSR switching approach is Cut Through. Thus, the combination offers the maximum performance and maximum compatibility with the standards. It provides MII/GMII/RGMII native interfaces for Ethernet PHY devices and it can be combined with Xilinx IP to support RMII or SGMII among other interfaces. It also supports and AXI4-Stream interface to be connected to other IP Cores that do not feature MAC based interfaces.

MES can be supported on the following Xilinx FPGA Families:

  • 6-Series (Spartan, Virtex)
  • 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
  • Ultrascale (Kintex, Virtex)
  • Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
- Managed Ethernet Switch IP Core for Xilinx Vivado Tool -

MES is designed to be easily integrated in your FPGA designs by taking advantage of the new Xilinx Vivado Tool, that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.

Managed Ethernet Switch IP Core key features:

Interfaces

  • Full-duplex 10/100/1000 Mbps Ethernet Interfaces
  • Half-duplex 10/100 Mbps Ethernet Interfaces
  • Full-duplex 10 Gbps Ethernet Interfaces (Under Development)
  • Configurable 3 to 32 Ethernet ports
  • MII/RMII/GMII/RGMII/SGMII/QSGMII Physical Layer device (PHY) interfaces
  • Different data rate supported for each port
  • Copper and Fiber optic media interfaces: 10/100/1000Base-T, 100Base-FX, 1000Base-X

Switching

  • Dynamic MAC Table with automatic MAC addresses learning and aging (up to 4096 entries)
  • Static MAC Table (up to 4096 entries)
  • Jumbo Frame Management
  • Ethertype Based Switching
  • Ingress Port Mirroring
  • Broadcast/Multicast Storm Protection
  • Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)

Time Synchronization

  • IEEE 1588v2 Stateless Transparent Clock functionality (P2P – Layer 2/ E2E – Layer 2)
  • Compatible with SoC-e IEEE 1588 IP Cores (1588Tiny, PreciseTimeBasic)

Traffic Management

  • Multicast Frame Filtering
  • Switching Portmask: User-defined forwarding of frames to concrete ports
  • Port-based VLAN support
  • QoS
    • Priorities (PCP-802.1p, DSCP TOS, Ethertype)
  • IEEE 802.1X EAPOL hardware processing
  • DSA (Distributed Switching Architecture) tagging: The ideal case for using DSA is when an Ethernet switch supports a “switch tag” which is a hardware feature making the switch insert a specific tag for each Ethernet frames it received to/from specific ports to help the management interface figure out:
    • What port is this frame coming from
    • What was the reason why this frame got forwarded
    • How to send CPU originated traffic to specific ports

Configuration

  • MDIO, UART, AXI4-Lite or CoE (Configuration-over-ethernet) management interfaces
  • Configuration-over-Ethernet (COE): Full access to internal registers through the same Ethernet link that connects to the CPU
  • Drivers are provided with IP Core purchase

Redundancy Protocols

  • RSTP (Software stack required)
    • Hardware support for RSTP
    • Reference RSTP stack for Linux provided with the IP Core
    • Posix  Compatible RSTP stack available
  • MRP (Software stack not required)
    • Ring Manager (MRM)
    • Ring Client (MRC)
  • DLR (Software stack not required)
    • Beacon Based Node
    • Supervisor Node

- Managed Ethernet Switch IP Core block diagram -

Supported boards for the Reference Designs:

  • SoC-e SMARTzynq brick (Recommended)
  • For other Xilinx/Avnet/SoC-e/ boards, we can provide a time-limited IP Core for evaluation

For more information, please contact us at: info@soc-e.com