Managed Ethernet Switch (MES) is an Ethernet switch IP Core targeted at programmable hardware platforms like FPGAs and reconfigurable SoCss

MES IP core features a non-blocking crossbar matrix that allows continuous transfers between all the ports. Implementing a Store & Forward switching approach, the switch buffers and verifies each frame before forwarding it. Besides, the latency time is in the order of nanoseconds. So, MES is the perfect switch to implement Ethernet based Industrial Networks.

Moreover, It can also be used in other applications. Thanks to the FPGA technology, our IP Cores are highly configurable, offering a wide range of options. In this case, our MES IP Core can go from a simple 3 port Ethernet Switch to a 32 port Ethernet Switch with QoS and RSTP for example.

MES can be combined with SoC-e’s IP Cores like the HSR-PRP Switch IP Core, introducing HSR and PRP capabilities in the ports in which it is required. HSR switching approach is Cut Through. Thus, the combination offers the greatest performance and compatibility with the standards.

Managed Ethernet Switch (MES) IP Core

Highly configurable Ethernet Switch

 

Managed Ethernet Switch IP Core key features

Interfaces

  • Full or Half duplex Ethernet Interfaces (up to 1Gbps)
  • 10 Gbps Ethernet Interfaces
  • Configurable 3 to 32 Ethernet ports
  • MII/RMII/GMII/RGMII/SGMII/QSGMII/USXGMII Physical Layer device (PHY) interfaces
  • Different data rates supported for each port
  • Copper and Fiber optic media interfaces: 10/100/1000Base-T, 100Base-FX, 1000Base-X

Switching

  • Dynamic or Static MAC Table  (up to 4096 entries)
  • Jumbo Frame Management
  • Ethertype Based Switching
  • Ingress Port Mirroring
  • Broadcast/Multicast Storm Protection
  • Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)

Configuration

  • MDIO, UART, AXI4-Lite or CoE (Configuration-over-ethernet)
  • Drivers are provided with IP Core purchase

Time Synchronization

  • IEEE 1588v2 Stateless Transparent Clock (P2P/E2E – Layer 2)
  • Compatible with SoC-e 1588v2 IP Cores (1588Tiny, PreciseTimeBasic)

Traffic Management

  • Multicast Frame Filtering
  • Switching Portmask: User-defined forwarding of frames to concrete ports
  • Port-based VLAN support
  • QoS
    • Priorities (PCP-802.1p, DSCP TOS, Ethertype)
  • IEEE 802.1X EAPOL hardware processing
  • DSA (Distributed Switching Architecture)

Redundancy Protocols

  • RSTP (Software stack required)
    • Hardware support for RSTP
    • Reference RSTP stack for Linux provided
    • Posix Compatible RSTP stack available
  • MRP (Software stack not required)
    • Ring Manager (MRM)
    • Ring Client (MRC)
  • DLR (Software stack not required)
    • Beacon Based Node
    • Supervisor Node

Managed Ethernet Switch (MES) IP Core block diagram

Managed Ethernet Switch IP Core block diagram

Supported Xilinx FPGA Families and Evaluation boards

Our MES IP Core can be deployed in the following Xilinx families. You can find the different Xilinx product tables and selection guides in the following links:

When it comes to Evaluation boards, at SoC-e we also develop System-on-Modules (SoMs) that we can provide with a preloaded design of our IP Cores. In this case, our recommendation would be the SMARTzynq brick solution, which has a 7-Series Zynq Xilinx FPGA. If the 7-Series Zynq device is not what you are looking for, we have other SoMs based on Ultrascale or Ultrascale+ Xilinx FPGA Families.

For other Xilinx/Avnet/SoC-e/ boards, we can provide a time-limited IP Core for evaluation

For more information, please contact us at: info@soc-e.com