How to optimize your FPGA resources when implementing large 1/10G Ethernet Switches?

The new 1/10G MES IP from SoC-e is a full-speed switching matrix supporting up to 32 ports. This multi-speed (100M/1G/2.5G/5G/10G) switch embeds a new micro-architecture focused on providing reliable operation even in the most demanding use-cases.

This IP is optimized for FPGA and reconfigurable SoCs.  SoC-e has developed an internal channel aggregation mechanism  to support switch implementations with a large number of 1G and 10G ports combined. This innovation offers FPGA logic savings larger than 40% for a switching matrix without this feature, reducing drastically the size of the required FPGA device.

The IP is fully integrated on Vivado IP to easy the integration of the IP in any design.

Thanks to 1/10G MES IP Industry-Scientific-Medical, Automotive and Aerospace&Defence sectors can benefit from a “real” 10G switching solution completed with the most demanded features in the projects of the sector:

  • Static and dynamic MAC table with independent VLAN learning
  • Flexible priorities scheme support
  • Full VLAN functionalities support
  • STP/RSTP/MSTP with up-to 4096 MSTIDs
  • Flexible port mirroring functionality at Ingress/Egress
  • Hardare IEEE 1588-PTP support: 1588 TC P2P/E2E  Layer 2

For more information, please visit 1/10G Managed Ethernet Switch IP web site.