New Optimized IP Core Portfolio for Digital Signal Processing Applications – December 2012 –

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Thanks to the new partnership between SoC-e and CEIT Research Center, we are proud to present a new set of high-optimized IP cores for Digital Signal Processing Applications implementable on Reconfigurable Logic. The first released core is the FFT/IFFF_Processor from a IP portfolio that includes IPs for Cordic, Interpolation, FIR filtering and Viterbi decoding.

More info at FPGA IP Cores for DSP Web page.