SoC-e at Embedded World 2016: SoC-e Smart Gateway

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Smart Factories require “Plug&Work” synchronized networking, distributed processing capabilities, heterogeneous sensor interfaces and layered cyber-security. SoC-e has run at Xilinx booth a demo that shows these capabilities based on Xilinx MPSoC devices, SoC-e switching and IEEE 1588v2 IPs and embedded sensor data processing (Juxt.io application).

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The block diagram of the demo is represented in the following block diagram:

 

SoCe_EW2016_MARKET_BLOCK_DIAGRAM__160208

 

The setup is composed by a 1GbE HSR Network that provides 0 seconds delay in case of network failure in the interconnection between smart devices and by a 1GbE network that attaches a Laptop and the bridge with Internet.

The three nodes connected in the HSR network include in the FPGA section SoC-e IP cores for networking and synchronization, and additionally each node runs the following functionalities:

  • Intelligent Gateway 1 (CPPS-gate40): It collects all the sensor data via Digital, Analog, Video and Serial interfaces of the emulated industrial setup. The data sensed at real-time are: Temperature (PT100), power consumption, grid frequency and harmonic distribution. This information is processed by the gateway internally using a Java application automatically generated using juxt.io platform. This application compares the status of the sensed industrial set-up, compress it with the model and forecast the failure point of the system. Additionally the results, graphs and actions (semaphore control) are done internally to the device. This information is remotely accessible from the Laptop and showed in the monitor.
  • Intelligent Gateway 2 (CPPS-gate40): It works as a Redundancy Box (RedBox) connection the HSR ring with the regular Ethernet network (the Laptop in the demo). Additionally, the IP core in charge of the networking runs deep hardware inspection blocking by hardware non authenticated traffic.
  • Central node: It is implemented using the new MPSoC device from Xilinx. SoC-e HSR/PRP IP core is supported in this new powerful platform that includes support for advances applications.

 

You can read more information about this show at Xilinx blog page.