SoC-e presents its low-latency IEEE 1588 UnmanagedEthernet Switch IP Core (UES) – July 2013 –

UES IP is an scalable and highly-optimized Ethernet Switch implementable on Xilinx families FPGAs. The switching structure is based on a full-crossbar interconection matrix between the ports. This approach ensures wire-speed frame processing and a very low latency times. The IP can include the support of optional features like IEEE 1588 Transparent Clock or Jumbo Frames.

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