In this new post, we will explain the degree of configuration that our IP Cores catalogue offers.
Our IP Cores are designed to be easily integrated in any FPGA design by taking advantage of the Xilinx Vivado Graphical User Interface (GUI), that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.
At SoC–e we have a wide experience programming these HDL generics in order to have this degree of configuration. We could say that for the case of switches, we have a “switch generator engine“.
In the case of MES IP Core, it offers these configurations:
- Interfaces: apart from PHY interfaces (MII/RMII/GMII/RGMII/SGMII/QSGMII), the switch offers different data rates for each port and Copper and Fiber optic media interfaces.
- Switching: Dynamic or Static MAC Table, Jumbo Frame Management, Ethertype Based Switching, Per-Port Rate limiting…
- Time Synchronization: IEEE 1588v2 Transparent Clock (P2P – Layer 2) option.
- Configuration: MDIO/UART/AXI4-Lite or CoE management interfaces.
- Traffic Management: Multicast Frame Filtering. Switching Portmask, Port-based VLAN support, QoS (Priorities), DSA.
- Redundancy Protocols: RSTP, MRP or DLR.
When it comes to our MTSN Switch IP Core, it offers almost the same switching configuration capabilities as our MES IP Core, adding these TSN configuration features:
- IEEE 802.1AS(rev): for Time Synchronization Layer.
- IEEE 802.1Qav: for Reserved Traffic.
- IEEE 802.1Qbv: for Scheduled Traffic.
- IEEE 802.1Qcc: for Network Management.
- IEEE 802.1Qci: for Stream Filtering and Policing.
- IEEE 802.1AB: for LLDP (Link Layer Discovery Protocol).
- IEEE 802.1w: for Rapid Spanning Tree Protocol.
- IEEE 802.1s: for Multiple Spanning Tree Protocol.
- IEEE 802.1CB: for Frame Replication and Elimination for Reliability.
- Cut-Through: support for Isochronous Scheduled Traffic.
- IEEE 802.1Qbu/802.3br: for Frame Preemtion
System-on-Chip engineering S.L. (SoC–e) is a worldwide leading supplier of time-aware Ethernet networking solutions. SoC-e is pioneer in developing a portfolio of IP cores and rugged platforms that implement these technologies for critical systems.
For more information, please contact us at: firstname.lastname@example.org