Visit SoC-e at Embedded World 2015 (Nuremberg, Germany) – February 2015

HSR Gigabit Ethernet QuadBox from Delta Networks released with network protocols IPs from SoC-e for Xilinx Zynq.

From the 24th to the 26th of February, SoC-e will be present at the 2015 Embedded world conference, held in Nuremberg, Germany. SoC-e will present jointly with Delta Networks NC (DNI) the HSR Gigabit Ethernet QuadBox released with network protocol IPs for Xilinx Zynq.


Delta Networks Inc (DNI), leading manufacturer of switching and networking equipment, and System-on-Chip engineering (SoC-e), expert engineering and design services for FPGAs and Embedded Systems, jointly present the first HSR QuadBox with Gigabit Ethernet and the new IEEE 1588 Power Utility Profile at the Xilinx booth (#209 in Hall 1) at the Embedded World 2015. This equipment uses protocols from IEC 62439-3, providing high network availability with zero-delay recovery time and hot-plug capability. The product is powered by Xilinx Zynq™-7000 and the HSR/PRP Switch IP core from SoC-e.


The two standards defined in IEC 62439-3, clauses 4 and 5, PRP (Parallel Redundancy Protocol) and HSR (High-availability Seamless Redundancy), provide resilient Layer-2 networking for Substation Automation and for Industrial Networking in general. As both standards work transparently to any higher level protocol, they are likewise suitable for other sectors such as Transportation or Aerospace. HSR has additional advantages concerning required space and operational cost because it omits switches from the network and provides redundancy using a single ring topology.

QuadBoxes allow connecting two HSR rings in the same network. Using two QuadBoxes avoids Single Point Failures in the network. Each QuadBox manages duplicated frames that cross from one ring to the other and circulates in both rings. The exhibited product from DNI supports configurations such as Smart RedBox (Redundancy Box) as well as modes to connect PRP and HSR networks.

Dual HSR rings network topology

- Figure 1: Dual HSR rings network topology -

Xilinx Zynq-7000 with the dual-core ARM® Cortex™-A9 MPCore™ processors and integrated FPGA technology, is perfectly suitable for the implementation of high-end smart network equipments. SoC-e’s HSR/PRP Switch IP is optimized for the implementation on Zynq. All HSR/PRP modes are supported as defined in IEC 62439-3, inclusive even of specific PRP-HSR and HSR-HSR modes. Hardware processing for IEEE 1588 Transparent Clock Peer-to-Peer (P2P) operates autonomously at each port (‘all-in-hardware’). Unique to this solution is a switching architecture that optionally applies cut-through operation for shortest queue times.


Full scalability of the switch and wire speed operation lowest latency are the key benefits of this solution. The solution can be complemented with any of the SoC-e portfolio IPs, like the all-in-one IEEE 1588 solution for Zynq or the Profinet and EtherNet IP/DLR IPs.


The live-demo at the Xilinx booth uses the two interlinked HSR sections. SoC-e’s ZYNQbox connects a network camera to the network. Two QuadBoxes from DNI provide the interconnection between two Gigabit Ethernet Networks with redundancy for high availability. A second ZYNQbox runs as a RedBox to connect to a laptop which receives the video stream from the remote camera. Losing link on any of the wires or even shutting down a whole QuadBox will not affect the communication

Live demo at Embedded World 2015_Image

- Figure 2: Live demo at Embedded World 2015 -

Mr. Jay Chan’s words, Industrial Network Manager from Delta DNI, summarizes the value of this proposal: “The benefits of HSR will rapidly influence many industrial sectors. Networks become very easy to manage, there is no need to implement any software stack to support the protocols and everything is inherently compatible with all applications that use Ethernet. Xilinx Zynq and SoC-e’s IPs allows the best flexibility and performance to address these markets with the maximum value”.

Find out more about our solutions and visit SoC-e at the Xilinx booth (#209 in Hall 1).