shutterstock_30744556_smallThe SoC-e PROFINET Switch IP core is an Intellectual Property (IP) Core for FPGAs. It co-works with a PROFINET software stack running on an external or an internal CPU (Microblaze or ARM9). This IP is an ideal solution for implementing flexible Profinet Automation equipments. The reference design implements PROFINET RT CC-B Line Structure integrating PORT.DE Profinet Software Stack.


Profinet Switch IP Core key functionalities are:

Port A and Port B: they are connected to a Profinet bus. They connect the equipment to a Line topology network.

Port C: it offers a conventional Ethernet link to any on-board or external CPU in order to receive Profinet frames.


- Profinet Switch IP Basic Structure -

The PROFINET Switch IP Core presents MII interface (10/100 Mbps) towards Interlink Port and towards External Ports connected to Ethernet PHYs. These ports have full-duplex interfaces.

The PROFINET Switch IP Core also presents MDIO interface in order to allow host CPU to access the registers of PROFINET Switch and to poll the status of the connected PHY devices.

The Profinet Switch IP Core includes the following functionalities:

  • This Profinet Switch IP Core supports up to four priority levels. Taking into account that there are eight priority levels in VLAN, these levels are accommodated two by two in the four priority queues that the core can support. This means that priorities zero and one are priority zero – zero being the smallest one – and priorities two and three are priority one, and so on. Nevertheless, the arrangement can be customized.
  • All the ports have four priority queues enabling four different priority levels. In the case of the External Ports, they have another four priority queues related with the forwarding process. Frames forwarded from one External Port to another one have priority over the frames that come from the interlink. Should there be a congestion situation, old frames are dropped from the priority queues.
  • The External Ports PHYs can be accessed from the CPU through a MDIO bus.
  • The Egress port can be selected by tagging the frames sent by the external CPU. There is also an auto-learning MAC table that helps to reduce the network load avoiding unnecessary duplication of frames.
  • The External CPU can write a static MAC table to forward all the frames with a matching destination MAC address to both interlink and the other External destination port.

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